`ifndef FIFO_IF__SV
`define FIFO_IF__SV
`timescale 1ns/1ns
interface fifo_if#(parameter WIDTH = 16);

  logic wrclk;
  logic rdclk;
  logic wr_rst_n;
  logic rd_rst_n;
  logic rd_en;
  logic wr_en;
  logic [WIDTH-1:0]wr_data;
  logic [WIDTH-1:0]rd_data;
  logic wr_full;
  logic rd_empty;
  
  reg   init_done;
  reg   wr_one_pkt;
  initial begin
    wrclk = 0;
	forever begin
	  #2 wrclk = ~wrclk;
	end
  end
  
  initial begin
    rdclk = 0;
	forever begin
	  #4 rdclk = ~rdclk;
	end
  end
  
  initial begin
    wr_rst_n = 1;
	rd_rst_n = 1;
	wr_en    = 0;
	rd_en    = 0;
	wr_data  = 'b0;
	init_done= 0;
	wr_one_pkt=0;
	
	#30 wr_rst_n = 0;
	    rd_rst_n = 0;
	#30 wr_rst_n = 1;
	    rd_rst_n = 1;
	
	#30 init_done = 1;
  end
  
  always@(*)begin
	if(init_done)begin
	  if(wr_full) wr_en = 0;
      else        wr_en = 1;  
	end
  end
  
  always@(*)begin
    if(init_done)begin
	  if(rd_empty) rd_en = 0;
	  else		   rd_en = 1;
	end
  end
  
  
endinterface:fifo_if
`endif
